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4665 pcplusmp open-codes register operations
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--- old/usr/src/uts/i86pc/io/pcplusmp/apic.c
+++ new/usr/src/uts/i86pc/io/pcplusmp/apic.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
31 31 */
32 32
33 33 /*
34 34 * To understand how the pcplusmp module interacts with the interrupt subsystem
35 35 * read the theory statement in uts/i86pc/os/intr.c.
36 36 */
37 37
38 38 /*
39 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42 42 * PSMI 1.5 extensions are supported in Solaris Nevada.
43 43 * PSMI 1.6 extensions are supported in Solaris Nevada.
44 44 * PSMI 1.7 extensions are supported in Solaris Nevada.
45 45 */
46 46 #define PSMI_1_7
47 47
48 48 #include <sys/processor.h>
49 49 #include <sys/time.h>
50 50 #include <sys/psm.h>
51 51 #include <sys/smp_impldefs.h>
52 52 #include <sys/cram.h>
53 53 #include <sys/acpi/acpi.h>
54 54 #include <sys/acpica.h>
55 55 #include <sys/psm_common.h>
56 56 #include <sys/apic.h>
57 57 #include <sys/pit.h>
58 58 #include <sys/ddi.h>
59 59 #include <sys/sunddi.h>
60 60 #include <sys/ddi_impldefs.h>
61 61 #include <sys/pci.h>
62 62 #include <sys/promif.h>
63 63 #include <sys/x86_archext.h>
64 64 #include <sys/cpc_impl.h>
65 65 #include <sys/uadmin.h>
66 66 #include <sys/panic.h>
67 67 #include <sys/debug.h>
68 68 #include <sys/archsystm.h>
69 69 #include <sys/trap.h>
70 70 #include <sys/machsystm.h>
71 71 #include <sys/sysmacros.h>
72 72 #include <sys/cpuvar.h>
73 73 #include <sys/rm_platter.h>
74 74 #include <sys/privregs.h>
75 75 #include <sys/note.h>
76 76 #include <sys/pci_intr_lib.h>
77 77 #include <sys/spl.h>
78 78 #include <sys/clock.h>
79 79 #include <sys/cyclic.h>
80 80 #include <sys/dditypes.h>
81 81 #include <sys/sunddi.h>
82 82 #include <sys/x_call.h>
83 83 #include <sys/reboot.h>
84 84 #include <sys/hpet.h>
85 85 #include <sys/apic_common.h>
86 86 #include <sys/apic_timer.h>
87 87
88 88 /*
89 89 * Local Function Prototypes
90 90 */
91 91 static void apic_init_intr(void);
92 92
93 93 /*
94 94 * standard MP entries
95 95 */
96 96 static int apic_probe(void);
97 97 static int apic_getclkirq(int ipl);
98 98 static void apic_init(void);
99 99 static void apic_picinit(void);
100 100 static int apic_post_cpu_start(void);
101 101 static int apic_intr_enter(int ipl, int *vect);
102 102 static void apic_setspl(int ipl);
103 103 static void x2apic_setspl(int ipl);
104 104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
105 105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
106 106 static int apic_disable_intr(processorid_t cpun);
107 107 static void apic_enable_intr(processorid_t cpun);
108 108 static int apic_get_ipivect(int ipl, int type);
109 109 static void apic_post_cyclic_setup(void *arg);
110 110
111 111 /*
112 112 * The following vector assignments influence the value of ipltopri and
113 113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
114 114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
115 115 * we care to do so in future. Note some IPLs which are rarely used
116 116 * will share the vector ranges and heavily used IPLs (5 and 6) have
117 117 * a wide range.
118 118 *
119 119 * This array is used to initialize apic_ipls[] (in apic_init()).
120 120 *
121 121 * IPL Vector range. as passed to intr_enter
122 122 * 0 none.
123 123 * 1,2,3 0x20-0x2f 0x0-0xf
124 124 * 4 0x30-0x3f 0x10-0x1f
125 125 * 5 0x40-0x5f 0x20-0x3f
126 126 * 6 0x60-0x7f 0x40-0x5f
127 127 * 7,8,9 0x80-0x8f 0x60-0x6f
128 128 * 10 0x90-0x9f 0x70-0x7f
129 129 * 11 0xa0-0xaf 0x80-0x8f
130 130 * ... ...
131 131 * 15 0xe0-0xef 0xc0-0xcf
132 132 * 15 0xf0-0xff 0xd0-0xdf
133 133 */
134 134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
135 135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
136 136 };
137 137 /*
138 138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
139 139 * NOTE that this is vector as passed into intr_enter which is
140 140 * programmed vector - 0x20 (APIC_BASE_VECT)
141 141 */
142 142
143 143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
144 144 /* The taskpri to be programmed into apic to mask given ipl */
145 145
146 146 /*
147 147 * Correlation of the hardware vector to the IPL in use, initialized
148 148 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
149 149 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
150 150 * connected to errata-stricken IOAPICs
151 151 */
152 152 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
153 153
154 154 /*
155 155 * Patchable global variables.
156 156 */
157 157 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
158 158 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
159 159
160 160 /*
161 161 * Local static data
162 162 */
163 163 static struct psm_ops apic_ops = {
164 164 apic_probe,
165 165
166 166 apic_init,
167 167 apic_picinit,
168 168 apic_intr_enter,
169 169 apic_intr_exit,
170 170 apic_setspl,
171 171 apic_addspl,
172 172 apic_delspl,
173 173 apic_disable_intr,
174 174 apic_enable_intr,
175 175 (int (*)(int))NULL, /* psm_softlvl_to_irq */
176 176 (void (*)(int))NULL, /* psm_set_softintr */
177 177
178 178 apic_set_idlecpu,
179 179 apic_unset_idlecpu,
180 180
181 181 apic_clkinit,
182 182 apic_getclkirq,
183 183 (void (*)(void))NULL, /* psm_hrtimeinit */
184 184 apic_gethrtime,
185 185
186 186 apic_get_next_processorid,
187 187 apic_cpu_start,
188 188 apic_post_cpu_start,
189 189 apic_shutdown,
190 190 apic_get_ipivect,
191 191 apic_send_ipi,
192 192
193 193 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
194 194 (void (*)(int, char *))NULL, /* psm_notify_error */
195 195 (void (*)(int))NULL, /* psm_notify_func */
196 196 apic_timer_reprogram,
197 197 apic_timer_enable,
198 198 apic_timer_disable,
199 199 apic_post_cyclic_setup,
200 200 apic_preshutdown,
201 201 apic_intr_ops, /* Advanced DDI Interrupt framework */
202 202 apic_state, /* save, restore apic state for S3 */
203 203 apic_cpu_ops, /* CPU control interface. */
204 204 };
205 205
206 206 struct psm_ops *psmops = &apic_ops;
207 207
208 208 static struct psm_info apic_psm_info = {
209 209 PSM_INFO_VER01_7, /* version */
210 210 PSM_OWN_EXCLUSIVE, /* ownership */
211 211 (struct psm_ops *)&apic_ops, /* operation */
212 212 APIC_PCPLUSMP_NAME, /* machine name */
213 213 "pcplusmp v1.4 compatible",
214 214 };
215 215
216 216 static void *apic_hdlp;
217 217
218 218 /*
219 219 * apic_let_idle_redistribute can have the following values:
220 220 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute.
221 221 * apic_redistribute_lock prevents multiple idle cpus from redistributing
222 222 */
223 223 int apic_num_idle_redistributions = 0;
224 224 static int apic_let_idle_redistribute = 0;
225 225
226 226 /* to gather intr data and redistribute */
227 227 static void apic_redistribute_compute(void);
228 228
229 229 /*
230 230 * This is the loadable module wrapper
231 231 */
232 232
233 233 int
234 234 _init(void)
235 235 {
236 236 if (apic_coarse_hrtime)
237 237 apic_ops.psm_gethrtime = &apic_gettime;
238 238 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
239 239 }
240 240
241 241 int
242 242 _fini(void)
243 243 {
244 244 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
245 245 }
246 246
247 247 int
248 248 _info(struct modinfo *modinfop)
249 249 {
250 250 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
251 251 }
252 252
253 253 static int
254 254 apic_probe(void)
255 255 {
256 256 /* check if apix is initialized */
257 257 if (apix_enable && apix_loaded())
258 258 return (PSM_FAILURE);
259 259 else
260 260 apix_enable = 0; /* continue using pcplusmp PSM */
261 261
262 262 return (apic_probe_common(apic_psm_info.p_mach_idstring));
263 263 }
264 264
265 265 static uchar_t
266 266 apic_xlate_vector_by_irq(uchar_t irq)
267 267 {
268 268 if (apic_irq_table[irq] == NULL)
269 269 return (0);
270 270
271 271 return (apic_irq_table[irq]->airq_vector);
272 272 }
273 273
274 274 void
275 275 apic_init(void)
276 276 {
277 277 int i;
278 278 int j = 1;
279 279
280 280 psm_get_ioapicid = apic_get_ioapicid;
281 281 psm_get_localapicid = apic_get_localapicid;
282 282 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
283 283
284 284 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
285 285 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
286 286 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
287 287 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
288 288 /* get to highest vector at the same ipl */
289 289 continue;
290 290 for (; j <= apic_vectortoipl[i]; j++) {
291 291 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
292 292 APIC_BASE_VECT;
293 293 }
294 294 }
295 295 for (; j < MAXIPL + 1; j++)
296 296 /* fill up any empty ipltopri slots */
297 297 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
298 298 apic_init_common();
299 299
300 300 #if !defined(__amd64)
301 301 if (cpuid_have_cr8access(CPU))
302 302 apic_have_32bit_cr8 = 1;
303 303 #endif
304 304 }
305 305
306 306 static void
307 307 apic_init_intr(void)
308 308 {
309 309 processorid_t cpun = psm_get_cpu_id();
310 310 uint_t nlvt;
311 311 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
312 312
313 313 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
314 314
315 315 if (apic_mode == LOCAL_APIC) {
316 316 /*
317 317 * We are running APIC in MMIO mode.
318 318 */
319 319 if (apic_flat_model) {
320 320 apic_reg_ops->apic_write(APIC_FORMAT_REG,
321 321 APIC_FLAT_MODEL);
322 322 } else {
323 323 apic_reg_ops->apic_write(APIC_FORMAT_REG,
324 324 APIC_CLUSTER_MODEL);
325 325 }
326 326
327 327 apic_reg_ops->apic_write(APIC_DEST_REG,
328 328 AV_HIGH_ORDER >> cpun);
329 329 }
330 330
331 331 if (apic_directed_EOI_supported()) {
332 332 /*
333 333 * Setting the 12th bit in the Spurious Interrupt Vector
334 334 * Register suppresses broadcast EOIs generated by the local
335 335 * APIC. The suppression of broadcast EOIs happens only when
336 336 * interrupts are level-triggered.
337 337 */
338 338 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
339 339 }
340 340
341 341 /* need to enable APIC before unmasking NMI */
342 342 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
343 343
344 344 /*
345 345 * Presence of an invalid vector with delivery mode AV_FIXED can
346 346 * cause an error interrupt, even if the entry is masked...so
347 347 * write a valid vector to LVT entries along with the mask bit
348 348 */
349 349
350 350 /* All APICs have timer and LINT0/1 */
351 351 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
352 352 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
353 353 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
354 354
355 355 /*
356 356 * On integrated APICs, the number of LVT entries is
357 357 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
358 358 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
359 359 */
360 360
361 361 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
362 362 nlvt = 3;
363 363 } else {
364 364 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
365 365 0xFF) + 1;
366 366 }
367 367
368 368 if (nlvt >= 5) {
369 369 /* Enable performance counter overflow interrupt */
370 370
371 371 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
372 372 apic_enable_cpcovf_intr = 0;
373 373 if (apic_enable_cpcovf_intr) {
374 374 if (apic_cpcovf_vect == 0) {
375 375 int ipl = APIC_PCINT_IPL;
376 376 int irq = apic_get_ipivect(ipl, -1);
377 377
378 378 ASSERT(irq != -1);
379 379 apic_cpcovf_vect =
380 380 apic_irq_table[irq]->airq_vector;
381 381 ASSERT(apic_cpcovf_vect);
382 382 (void) add_avintr(NULL, ipl,
383 383 (avfunc)kcpc_hw_overflow_intr,
384 384 "apic pcint", irq, NULL, NULL, NULL, NULL);
385 385 kcpc_hw_overflow_intr_installed = 1;
386 386 kcpc_hw_enable_cpc_intr =
387 387 apic_cpcovf_mask_clear;
388 388 }
389 389 apic_reg_ops->apic_write(APIC_PCINT_VECT,
390 390 apic_cpcovf_vect);
391 391 }
392 392 }
393 393
394 394 if (nlvt >= 6) {
395 395 /* Only mask TM intr if the BIOS apparently doesn't use it */
396 396
397 397 uint32_t lvtval;
398 398
399 399 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
400 400 if (((lvtval & AV_MASK) == AV_MASK) ||
401 401 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
402 402 apic_reg_ops->apic_write(APIC_THERM_VECT,
403 403 AV_MASK|APIC_RESV_IRQ);
404 404 }
405 405 }
406 406
407 407 /* Enable error interrupt */
408 408
409 409 if (nlvt >= 4 && apic_enable_error_intr) {
410 410 if (apic_errvect == 0) {
411 411 int ipl = 0xf; /* get highest priority intr */
412 412 int irq = apic_get_ipivect(ipl, -1);
413 413
414 414 ASSERT(irq != -1);
415 415 apic_errvect = apic_irq_table[irq]->airq_vector;
416 416 ASSERT(apic_errvect);
417 417 /*
418 418 * Not PSMI compliant, but we are going to merge
419 419 * with ON anyway
420 420 */
421 421 (void) add_avintr((void *)NULL, ipl,
422 422 (avfunc)apic_error_intr, "apic error intr",
423 423 irq, NULL, NULL, NULL, NULL);
424 424 }
425 425 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
426 426 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
427 427 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
428 428 }
429 429
430 430 /* Enable CMCI interrupt */
431 431 if (cmi_enable_cmci) {
432 432
433 433 mutex_enter(&cmci_cpu_setup_lock);
434 434 if (cmci_cpu_setup_registered == 0) {
435 435 mutex_enter(&cpu_lock);
436 436 register_cpu_setup_func(cmci_cpu_setup, NULL);
437 437 mutex_exit(&cpu_lock);
438 438 cmci_cpu_setup_registered = 1;
439 439 }
440 440 mutex_exit(&cmci_cpu_setup_lock);
441 441
442 442 if (apic_cmci_vect == 0) {
443 443 int ipl = 0x2;
444 444 int irq = apic_get_ipivect(ipl, -1);
445 445
446 446 ASSERT(irq != -1);
447 447 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
448 448 ASSERT(apic_cmci_vect);
449 449
450 450 (void) add_avintr(NULL, ipl,
451 451 (avfunc)cmi_cmci_trap,
452 452 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
453 453 }
454 454 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
455 455 }
456 456 }
457 457
458 458 static void
459 459 apic_picinit(void)
460 460 {
461 461 int i, j;
462 462 uint_t isr;
463 463
464 464 /*
465 465 * Initialize and enable interrupt remapping before apic
466 466 * hardware initialization
467 467 */
468 468 apic_intrmap_init(apic_mode);
469 469
470 470 /*
471 471 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
472 472 * bit on without clearing it with EOI. Since softint
473 473 * uses vector 0x20 to interrupt itself, so softint will
474 474 * not work on this machine. In order to fix this problem
475 475 * a check is made to verify all the isr bits are clear.
476 476 * If not, EOIs are issued to clear the bits.
477 477 */
478 478 for (i = 7; i >= 1; i--) {
479 479 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
480 480 if (isr != 0)
481 481 for (j = 0; ((j < 32) && (isr != 0)); j++)
482 482 if (isr & (1 << j)) {
483 483 apic_reg_ops->apic_write(
484 484 APIC_EOI_REG, 0);
485 485 isr &= ~(1 << j);
486 486 apic_error |= APIC_ERR_BOOT_EOI;
487 487 }
488 488 }
489 489
490 490 /* set a flag so we know we have run apic_picinit() */
491 491 apic_picinit_called = 1;
492 492 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
493 493 LOCK_INIT_CLEAR(&apic_ioapic_lock);
494 494 LOCK_INIT_CLEAR(&apic_error_lock);
495 495 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
496 496
497 497 picsetup(); /* initialise the 8259 */
498 498
499 499 /* add nmi handler - least priority nmi handler */
500 500 LOCK_INIT_CLEAR(&apic_nmi_lock);
501 501
502 502 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
503 503 "pcplusmp NMI handler", (caddr_t)NULL))
504 504 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
505 505
506 506 /*
507 507 * Check for directed-EOI capability in the local APIC.
508 508 */
509 509 if (apic_directed_EOI_supported() == 1) {
510 510 apic_set_directed_EOI_handler();
511 511 }
512 512
513 513 apic_init_intr();
514 514
515 515 /* enable apic mode if imcr present */
516 516 if (apic_imcrp) {
517 517 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
518 518 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
519 519 }
520 520
521 521 ioapic_init_intr(IOAPIC_MASK);
522 522 }
523 523
524 524 #ifdef DEBUG
525 525 void
526 526 apic_break(void)
527 527 {
528 528 }
529 529 #endif /* DEBUG */
530 530
531 531 /*
532 532 * platform_intr_enter
533 533 *
534 534 * Called at the beginning of the interrupt service routine to
535 535 * mask all level equal to and below the interrupt priority
536 536 * of the interrupting vector. An EOI should be given to
537 537 * the interrupt controller to enable other HW interrupts.
538 538 *
539 539 * Return -1 for spurious interrupts
540 540 *
541 541 */
542 542 /*ARGSUSED*/
543 543 static int
544 544 apic_intr_enter(int ipl, int *vectorp)
545 545 {
546 546 uchar_t vector;
547 547 int nipl;
548 548 int irq;
549 549 ulong_t iflag;
550 550 apic_cpus_info_t *cpu_infop;
551 551
552 552 /*
553 553 * The real vector delivered is (*vectorp + 0x20), but our caller
554 554 * subtracts 0x20 from the vector before passing it to us.
555 555 * (That's why APIC_BASE_VECT is 0x20.)
556 556 */
557 557 vector = (uchar_t)*vectorp;
558 558
559 559 /* if interrupted by the clock, increment apic_nsec_since_boot */
560 560 if (vector == apic_clkvect) {
561 561 if (!apic_oneshot) {
562 562 /* NOTE: this is not MT aware */
563 563 apic_hrtime_stamp++;
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563 lines elided |
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564 564 apic_nsec_since_boot += apic_nsec_per_intr;
565 565 apic_hrtime_stamp++;
566 566 last_count_read = apic_hertz_count;
567 567 apic_redistribute_compute();
568 568 }
569 569
570 570 /* We will avoid all the book keeping overhead for clock */
571 571 nipl = apic_ipls[vector];
572 572
573 573 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
574 - if (apic_mode == LOCAL_APIC) {
575 -#if defined(__amd64)
576 - setcr8((ulong_t)(apic_ipltopri[nipl] >>
577 - APIC_IPL_SHIFT));
578 -#else
579 - if (apic_have_32bit_cr8)
580 - setcr8((ulong_t)(apic_ipltopri[nipl] >>
581 - APIC_IPL_SHIFT));
582 - else
583 - LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
584 - (uint32_t)apic_ipltopri[nipl]);
585 -#endif
586 - LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
587 - } else {
588 - X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
589 - X2APIC_WRITE(APIC_EOI_REG, 0);
590 - }
574 +
575 + apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
576 + apic_reg_ops->apic_send_eoi(0);
591 577
592 578 return (nipl);
593 579 }
594 580
595 581 cpu_infop = &apic_cpus[psm_get_cpu_id()];
596 582
597 583 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
598 584 cpu_infop->aci_spur_cnt++;
599 585 return (APIC_INT_SPURIOUS);
600 586 }
601 587
602 588 /* Check if the vector we got is really what we need */
603 589 if (apic_revector_pending) {
604 590 /*
605 591 * Disable interrupts for the duration of
606 592 * the vector translation to prevent a self-race for
607 593 * the apic_revector_lock. This cannot be done
608 594 * in apic_xlate_vector because it is recursive and
609 595 * we want the vector translation to be atomic with
610 596 * respect to other (higher-priority) interrupts.
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611 597 */
612 598 iflag = intr_clear();
613 599 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
614 600 APIC_BASE_VECT;
615 601 intr_restore(iflag);
616 602 }
617 603
618 604 nipl = apic_ipls[vector];
619 605 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
620 606
621 - if (apic_mode == LOCAL_APIC) {
622 -#if defined(__amd64)
623 - setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT));
624 -#else
625 - if (apic_have_32bit_cr8)
626 - setcr8((ulong_t)(apic_ipltopri[nipl] >>
627 - APIC_IPL_SHIFT));
628 - else
629 - LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
630 - (uint32_t)apic_ipltopri[nipl]);
631 -#endif
632 - } else {
633 - X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
634 - }
607 + apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
635 608
636 609 cpu_infop->aci_current[nipl] = (uchar_t)irq;
637 610 cpu_infop->aci_curipl = (uchar_t)nipl;
638 611 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
639 612
640 613 /*
641 614 * apic_level_intr could have been assimilated into the irq struct.
642 615 * but, having it as a character array is more efficient in terms of
643 616 * cache usage. So, we leave it as is.
644 617 */
645 618 if (!apic_level_intr[irq]) {
646 - if (apic_mode == LOCAL_APIC) {
647 - LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
648 - } else {
649 - X2APIC_WRITE(APIC_EOI_REG, 0);
650 - }
619 + apic_reg_ops->apic_send_eoi(0);
651 620 }
652 621
653 622 #ifdef DEBUG
654 623 APIC_DEBUG_BUF_PUT(vector);
655 624 APIC_DEBUG_BUF_PUT(irq);
656 625 APIC_DEBUG_BUF_PUT(nipl);
657 626 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
658 627 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
659 628 drv_usecwait(apic_stretch_interrupts);
660 629
661 630 if (apic_break_on_cpu == psm_get_cpu_id())
662 631 apic_break();
663 632 #endif /* DEBUG */
664 633 return (nipl);
665 634 }
666 635
667 636 /*
668 637 * This macro is a common code used by MMIO local apic and X2APIC
669 638 * local apic.
670 639 */
671 640 #define APIC_INTR_EXIT() \
672 641 { \
673 642 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \
674 643 if (apic_level_intr[irq]) \
675 644 apic_reg_ops->apic_send_eoi(irq); \
676 645 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \
677 646 /* ISR above current pri could not be in progress */ \
678 647 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \
679 648 }
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680 649
681 650 /*
682 651 * Any changes made to this function must also change X2APIC
683 652 * version of intr_exit.
684 653 */
685 654 void
686 655 apic_intr_exit(int prev_ipl, int irq)
687 656 {
688 657 apic_cpus_info_t *cpu_infop;
689 658
690 -#if defined(__amd64)
691 - setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
692 -#else
693 - if (apic_have_32bit_cr8)
694 - setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
695 - else
696 - apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl];
697 -#endif
659 + apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]);
698 660
699 661 APIC_INTR_EXIT();
700 662 }
701 663
702 664 /*
703 665 * Same as apic_intr_exit() except it uses MSR rather than MMIO
704 666 * to access local apic registers.
705 667 */
706 668 void
707 669 x2apic_intr_exit(int prev_ipl, int irq)
708 670 {
709 671 apic_cpus_info_t *cpu_infop;
710 672
711 673 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]);
712 674 APIC_INTR_EXIT();
713 675 }
714 676
715 677 intr_exit_fn_t
716 678 psm_intr_exit_fn(void)
717 679 {
718 680 if (apic_mode == LOCAL_X2APIC)
719 681 return (x2apic_intr_exit);
720 682
721 683 return (apic_intr_exit);
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722 684 }
723 685
724 686 /*
725 687 * Mask all interrupts below or equal to the given IPL.
726 688 * Any changes made to this function must also change X2APIC
727 689 * version of setspl.
728 690 */
729 691 static void
730 692 apic_setspl(int ipl)
731 693 {
732 -#if defined(__amd64)
733 - setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
734 -#else
735 - if (apic_have_32bit_cr8)
736 - setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
737 - else
738 - apicadr[APIC_TASK_REG] = apic_ipltopri[ipl];
739 -#endif
694 + apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]);
740 695
741 696 /* interrupts at ipl above this cannot be in progress */
742 697 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
743 698 /*
744 699 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
745 700 * have enough time to come in before the priority is raised again
746 701 * during the idle() loop.
747 702 */
748 703 if (apic_setspl_delay)
749 704 (void) apic_reg_ops->apic_get_pri();
750 705 }
751 706
752 707 /*
753 708 * X2APIC version of setspl.
754 709 * Mask all interrupts below or equal to the given IPL
755 710 */
756 711 static void
757 712 x2apic_setspl(int ipl)
758 713 {
759 714 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]);
760 715
761 716 /* interrupts at ipl above this cannot be in progress */
762 717 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
763 718 }
764 719
765 720 /*ARGSUSED*/
766 721 static int
767 722 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
768 723 {
769 724 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
770 725 }
771 726
772 727 static int
773 728 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
774 729 {
775 730 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
776 731 }
777 732
778 733 static int
779 734 apic_post_cpu_start(void)
780 735 {
781 736 int cpun;
782 737 static int cpus_started = 1;
783 738
784 739 /* We know this CPU + BSP started successfully. */
785 740 cpus_started++;
786 741
787 742 /*
788 743 * On BSP we would have enabled X2APIC, if supported by processor,
789 744 * in acpi_probe(), but on AP we do it here.
790 745 *
791 746 * We enable X2APIC mode only if BSP is running in X2APIC & the
792 747 * local APIC mode of the current CPU is MMIO (xAPIC).
793 748 */
794 749 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
795 750 apic_local_mode() == LOCAL_APIC) {
796 751 apic_enable_x2apic();
797 752 }
798 753
799 754 /*
800 755 * Switch back to x2apic IPI sending method for performance when target
801 756 * CPU has entered x2apic mode.
802 757 */
803 758 if (apic_mode == LOCAL_X2APIC) {
804 759 apic_switch_ipi_callback(B_FALSE);
805 760 }
806 761
807 762 splx(ipltospl(LOCK_LEVEL));
808 763 apic_init_intr();
809 764
810 765 /*
811 766 * since some systems don't enable the internal cache on the non-boot
812 767 * cpus, so we have to enable them here
813 768 */
814 769 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
815 770
816 771 #ifdef DEBUG
817 772 APIC_AV_PENDING_SET();
818 773 #else
819 774 if (apic_mode == LOCAL_APIC)
820 775 APIC_AV_PENDING_SET();
821 776 #endif /* DEBUG */
822 777
823 778 /*
824 779 * We may be booting, or resuming from suspend; aci_status will
825 780 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
826 781 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
827 782 */
828 783 cpun = psm_get_cpu_id();
829 784 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
830 785
831 786 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
832 787 return (PSM_SUCCESS);
833 788 }
834 789
835 790 /*
836 791 * type == -1 indicates it is an internal request. Do not change
837 792 * resv_vector for these requests
838 793 */
839 794 static int
840 795 apic_get_ipivect(int ipl, int type)
841 796 {
842 797 uchar_t vector;
843 798 int irq;
844 799
845 800 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
846 801 if (vector = apic_allocate_vector(ipl, irq, 1)) {
847 802 apic_irq_table[irq]->airq_mps_intr_index =
848 803 RESERVE_INDEX;
849 804 apic_irq_table[irq]->airq_vector = vector;
850 805 if (type != -1) {
851 806 apic_resv_vector[ipl] = vector;
852 807 }
853 808 return (irq);
854 809 }
855 810 }
856 811 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
857 812 return (-1); /* shouldn't happen */
858 813 }
859 814
860 815 static int
861 816 apic_getclkirq(int ipl)
862 817 {
863 818 int irq;
864 819
865 820 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
866 821 return (-1);
867 822 /*
868 823 * Note the vector in apic_clkvect for per clock handling.
869 824 */
870 825 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
871 826 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
872 827 apic_clkvect));
873 828 return (irq);
874 829 }
875 830
876 831 /*
877 832 * Try and disable all interrupts. We just assign interrupts to other
878 833 * processors based on policy. If any were bound by user request, we
879 834 * let them continue and return failure. We do not bother to check
880 835 * for cache affinity while rebinding.
881 836 */
882 837
883 838 static int
884 839 apic_disable_intr(processorid_t cpun)
885 840 {
886 841 int bind_cpu = 0, i, hardbound = 0;
887 842 apic_irq_t *irq_ptr;
888 843 ulong_t iflag;
889 844
890 845 iflag = intr_clear();
891 846 lock_set(&apic_ioapic_lock);
892 847
893 848 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
894 849 if (apic_reprogram_info[i].done == B_FALSE) {
895 850 if (apic_reprogram_info[i].bindcpu == cpun) {
896 851 /*
897 852 * CPU is busy -- it's the target of
898 853 * a pending reprogramming attempt
899 854 */
900 855 lock_clear(&apic_ioapic_lock);
901 856 intr_restore(iflag);
902 857 return (PSM_FAILURE);
903 858 }
904 859 }
905 860 }
906 861
907 862 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
908 863
909 864 apic_cpus[cpun].aci_curipl = 0;
910 865
911 866 i = apic_min_device_irq;
912 867 for (; i <= apic_max_device_irq; i++) {
913 868 /*
914 869 * If there are bound interrupts on this cpu, then
915 870 * rebind them to other processors.
916 871 */
917 872 if ((irq_ptr = apic_irq_table[i]) != NULL) {
918 873 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
919 874 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
920 875 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
921 876
922 877 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
923 878 hardbound = 1;
924 879 continue;
925 880 }
926 881
927 882 if (irq_ptr->airq_temp_cpu == cpun) {
928 883 do {
929 884 bind_cpu =
930 885 apic_find_cpu(APIC_CPU_INTR_ENABLE);
931 886 } while (apic_rebind_all(irq_ptr, bind_cpu));
932 887 }
933 888 }
934 889 }
935 890
936 891 lock_clear(&apic_ioapic_lock);
937 892 intr_restore(iflag);
938 893
939 894 if (hardbound) {
940 895 cmn_err(CE_WARN, "Could not disable interrupts on %d"
941 896 "due to user bound interrupts", cpun);
942 897 return (PSM_FAILURE);
943 898 }
944 899 else
945 900 return (PSM_SUCCESS);
946 901 }
947 902
948 903 /*
949 904 * Bind interrupts to the CPU's local APIC.
950 905 * Interrupts should not be bound to a CPU's local APIC until the CPU
951 906 * is ready to receive interrupts.
952 907 */
953 908 static void
954 909 apic_enable_intr(processorid_t cpun)
955 910 {
956 911 int i;
957 912 apic_irq_t *irq_ptr;
958 913 ulong_t iflag;
959 914
960 915 iflag = intr_clear();
961 916 lock_set(&apic_ioapic_lock);
962 917
963 918 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
964 919
965 920 i = apic_min_device_irq;
966 921 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
967 922 if ((irq_ptr = apic_irq_table[i]) != NULL) {
968 923 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
969 924 (void) apic_rebind_all(irq_ptr,
970 925 irq_ptr->airq_cpu);
971 926 }
972 927 }
973 928 }
974 929
975 930 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
976 931 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
977 932
978 933 lock_clear(&apic_ioapic_lock);
979 934 intr_restore(iflag);
980 935 }
981 936
982 937 /*
983 938 * If this module needs a periodic handler for the interrupt distribution, it
984 939 * can be added here. The argument to the periodic handler is not currently
985 940 * used, but is reserved for future.
986 941 */
987 942 static void
988 943 apic_post_cyclic_setup(void *arg)
989 944 {
990 945 _NOTE(ARGUNUSED(arg))
991 946
992 947 cyc_handler_t cyh;
993 948 cyc_time_t cyt;
994 949
995 950 /* cpu_lock is held */
996 951 /* set up a periodic handler for intr redistribution */
997 952
998 953 /*
999 954 * In peridoc mode intr redistribution processing is done in
1000 955 * apic_intr_enter during clk intr processing
1001 956 */
1002 957 if (!apic_oneshot)
1003 958 return;
1004 959
1005 960 /*
1006 961 * Register a periodical handler for the redistribution processing.
1007 962 * Though we would generally prefer to use the DDI interface for
1008 963 * periodic handler invocation, ddi_periodic_add(9F), we are
1009 964 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1010 965 * attempt to take for us. Thus, we add our own cyclic directly:
1011 966 */
1012 967 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
1013 968 cyh.cyh_arg = NULL;
1014 969 cyh.cyh_level = CY_LOW_LEVEL;
1015 970
1016 971 cyt.cyt_when = 0;
1017 972 cyt.cyt_interval = apic_redistribute_sample_interval;
1018 973
1019 974 apic_cyclic_id = cyclic_add(&cyh, &cyt);
1020 975 }
1021 976
1022 977 static void
1023 978 apic_redistribute_compute(void)
1024 979 {
1025 980 int i, j, max_busy;
1026 981
1027 982 if (apic_enable_dynamic_migration) {
1028 983 if (++apic_nticks == apic_sample_factor_redistribution) {
1029 984 /*
1030 985 * Time to call apic_intr_redistribute().
1031 986 * reset apic_nticks. This will cause max_busy
1032 987 * to be calculated below and if it is more than
1033 988 * apic_int_busy, we will do the whole thing
1034 989 */
1035 990 apic_nticks = 0;
1036 991 }
1037 992 max_busy = 0;
1038 993 for (i = 0; i < apic_nproc; i++) {
1039 994 if (!apic_cpu_in_range(i))
1040 995 continue;
1041 996
1042 997 /*
1043 998 * Check if curipl is non zero & if ISR is in
1044 999 * progress
1045 1000 */
1046 1001 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1047 1002 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1048 1003
1049 1004 int irq;
1050 1005 apic_cpus[i].aci_busy++;
1051 1006 irq = apic_cpus[i].aci_current[j];
1052 1007 apic_irq_table[irq]->airq_busy++;
1053 1008 }
1054 1009
1055 1010 if (!apic_nticks &&
1056 1011 (apic_cpus[i].aci_busy > max_busy))
1057 1012 max_busy = apic_cpus[i].aci_busy;
1058 1013 }
1059 1014 if (!apic_nticks) {
1060 1015 if (max_busy > apic_int_busy_mark) {
1061 1016 /*
1062 1017 * We could make the following check be
1063 1018 * skipped > 1 in which case, we get a
1064 1019 * redistribution at half the busy mark (due to
1065 1020 * double interval). Need to be able to collect
1066 1021 * more empirical data to decide if that is a
1067 1022 * good strategy. Punt for now.
1068 1023 */
1069 1024 if (apic_skipped_redistribute) {
1070 1025 apic_cleanup_busy();
1071 1026 apic_skipped_redistribute = 0;
1072 1027 } else {
1073 1028 apic_intr_redistribute();
1074 1029 }
1075 1030 } else
1076 1031 apic_skipped_redistribute++;
1077 1032 }
1078 1033 }
1079 1034 }
1080 1035
1081 1036
1082 1037 /*
1083 1038 * The following functions are in the platform specific file so that they
1084 1039 * can be different functions depending on whether we are running on
1085 1040 * bare metal or a hypervisor.
1086 1041 */
1087 1042
1088 1043 /*
1089 1044 * Check to make sure there are enough irq slots
1090 1045 */
1091 1046 int
1092 1047 apic_check_free_irqs(int count)
1093 1048 {
1094 1049 int i, avail;
1095 1050
1096 1051 avail = 0;
1097 1052 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1098 1053 if ((apic_irq_table[i] == NULL) ||
1099 1054 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
1100 1055 if (++avail >= count)
1101 1056 return (PSM_SUCCESS);
1102 1057 }
1103 1058 }
1104 1059 return (PSM_FAILURE);
1105 1060 }
1106 1061
1107 1062 /*
1108 1063 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
1109 1064 */
1110 1065 int
1111 1066 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
1112 1067 int behavior)
1113 1068 {
1114 1069 int rcount, i;
1115 1070 uchar_t start, irqno;
1116 1071 uint32_t cpu;
1117 1072 major_t major;
1118 1073 apic_irq_t *irqptr;
1119 1074
1120 1075 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1121 1076 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1122 1077 (void *)dip, inum, pri, count, behavior));
1123 1078
1124 1079 if (count > 1) {
1125 1080 if (behavior == DDI_INTR_ALLOC_STRICT &&
1126 1081 apic_multi_msi_enable == 0)
1127 1082 return (0);
1128 1083 if (apic_multi_msi_enable == 0)
1129 1084 count = 1;
1130 1085 }
1131 1086
1132 1087 if ((rcount = apic_navail_vector(dip, pri)) > count)
1133 1088 rcount = count;
1134 1089 else if (rcount == 0 || (rcount < count &&
1135 1090 behavior == DDI_INTR_ALLOC_STRICT))
1136 1091 return (0);
1137 1092
1138 1093 /* if not ISP2, then round it down */
1139 1094 if (!ISP2(rcount))
1140 1095 rcount = 1 << (highbit(rcount) - 1);
1141 1096
1142 1097 mutex_enter(&airq_mutex);
1143 1098
1144 1099 for (start = 0; rcount > 0; rcount >>= 1) {
1145 1100 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1146 1101 behavior == DDI_INTR_ALLOC_STRICT)
1147 1102 break;
1148 1103 }
1149 1104
1150 1105 if (start == 0) {
1151 1106 /* no vector available */
1152 1107 mutex_exit(&airq_mutex);
1153 1108 return (0);
1154 1109 }
1155 1110
1156 1111 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1157 1112 /* not enough free irq slots available */
1158 1113 mutex_exit(&airq_mutex);
1159 1114 return (0);
1160 1115 }
1161 1116
1162 1117 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1163 1118 for (i = 0; i < rcount; i++) {
1164 1119 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1165 1120 (uchar_t)-1) {
1166 1121 /*
1167 1122 * shouldn't happen because of the
1168 1123 * apic_check_free_irqs() check earlier
1169 1124 */
1170 1125 mutex_exit(&airq_mutex);
1171 1126 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1172 1127 "apic_allocate_irq failed\n"));
1173 1128 return (i);
1174 1129 }
1175 1130 apic_max_device_irq = max(irqno, apic_max_device_irq);
1176 1131 apic_min_device_irq = min(irqno, apic_min_device_irq);
1177 1132 irqptr = apic_irq_table[irqno];
1178 1133 #ifdef DEBUG
1179 1134 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1180 1135 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1181 1136 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1182 1137 #endif
1183 1138 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1184 1139
1185 1140 irqptr->airq_vector = (uchar_t)(start + i);
1186 1141 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1187 1142 irqptr->airq_intin_no = (uchar_t)rcount;
1188 1143 irqptr->airq_ipl = pri;
1189 1144 irqptr->airq_vector = start + i;
1190 1145 irqptr->airq_origirq = (uchar_t)(inum + i);
1191 1146 irqptr->airq_share_id = 0;
1192 1147 irqptr->airq_mps_intr_index = MSI_INDEX;
1193 1148 irqptr->airq_dip = dip;
1194 1149 irqptr->airq_major = major;
1195 1150 if (i == 0) /* they all bound to the same cpu */
1196 1151 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1197 1152 0xff, 0xff);
1198 1153 else
1199 1154 irqptr->airq_cpu = cpu;
1200 1155 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1201 1156 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1202 1157 (void *)irqptr->airq_dip, irqptr->airq_vector,
1203 1158 irqptr->airq_origirq, pri));
1204 1159 }
1205 1160 mutex_exit(&airq_mutex);
1206 1161 return (rcount);
1207 1162 }
1208 1163
1209 1164 /*
1210 1165 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1211 1166 */
1212 1167 int
1213 1168 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1214 1169 int behavior)
1215 1170 {
1216 1171 int rcount, i;
1217 1172 major_t major;
1218 1173
1219 1174 mutex_enter(&airq_mutex);
1220 1175
1221 1176 if ((rcount = apic_navail_vector(dip, pri)) > count)
1222 1177 rcount = count;
1223 1178 else if (rcount == 0 || (rcount < count &&
1224 1179 behavior == DDI_INTR_ALLOC_STRICT)) {
1225 1180 rcount = 0;
1226 1181 goto out;
1227 1182 }
1228 1183
1229 1184 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1230 1185 /* not enough free irq slots available */
1231 1186 rcount = 0;
1232 1187 goto out;
1233 1188 }
1234 1189
1235 1190 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1236 1191 for (i = 0; i < rcount; i++) {
1237 1192 uchar_t vector, irqno;
1238 1193 apic_irq_t *irqptr;
1239 1194
1240 1195 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1241 1196 (uchar_t)-1) {
1242 1197 /*
1243 1198 * shouldn't happen because of the
1244 1199 * apic_check_free_irqs() check earlier
1245 1200 */
1246 1201 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1247 1202 "apic_allocate_irq failed\n"));
1248 1203 rcount = i;
1249 1204 goto out;
1250 1205 }
1251 1206 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1252 1207 /*
1253 1208 * shouldn't happen because of the
1254 1209 * apic_navail_vector() call earlier
1255 1210 */
1256 1211 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1257 1212 "apic_allocate_vector failed\n"));
1258 1213 rcount = i;
1259 1214 goto out;
1260 1215 }
1261 1216 apic_max_device_irq = max(irqno, apic_max_device_irq);
1262 1217 apic_min_device_irq = min(irqno, apic_min_device_irq);
1263 1218 irqptr = apic_irq_table[irqno];
1264 1219 irqptr->airq_vector = (uchar_t)vector;
1265 1220 irqptr->airq_ipl = pri;
1266 1221 irqptr->airq_origirq = (uchar_t)(inum + i);
1267 1222 irqptr->airq_share_id = 0;
1268 1223 irqptr->airq_mps_intr_index = MSIX_INDEX;
1269 1224 irqptr->airq_dip = dip;
1270 1225 irqptr->airq_major = major;
1271 1226 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1272 1227 }
1273 1228 out:
1274 1229 mutex_exit(&airq_mutex);
1275 1230 return (rcount);
1276 1231 }
1277 1232
1278 1233 /*
1279 1234 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1280 1235 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1281 1236 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1282 1237 * requests and allocated only when pri is set.
1283 1238 */
1284 1239 uchar_t
1285 1240 apic_allocate_vector(int ipl, int irq, int pri)
1286 1241 {
1287 1242 int lowest, highest, i;
1288 1243
1289 1244 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1290 1245 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1291 1246
1292 1247 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1293 1248 lowest -= APIC_VECTOR_PER_IPL;
1294 1249
1295 1250 #ifdef DEBUG
1296 1251 if (apic_restrict_vector) /* for testing shared interrupt logic */
1297 1252 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1298 1253 #endif /* DEBUG */
1299 1254 if (pri == 0)
1300 1255 highest -= APIC_HI_PRI_VECTS;
1301 1256
1302 1257 for (i = lowest; i <= highest; i++) {
1303 1258 if (APIC_CHECK_RESERVE_VECTORS(i))
1304 1259 continue;
1305 1260 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1306 1261 apic_vector_to_irq[i] = (uchar_t)irq;
1307 1262 return (i);
1308 1263 }
1309 1264 }
1310 1265
1311 1266 return (0);
1312 1267 }
1313 1268
1314 1269 /* Mark vector as not being used by any irq */
1315 1270 void
1316 1271 apic_free_vector(uchar_t vector)
1317 1272 {
1318 1273 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1319 1274 }
1320 1275
1321 1276 /*
1322 1277 * Call rebind to do the actual programming.
1323 1278 * Must be called with interrupts disabled and apic_ioapic_lock held
1324 1279 * 'p' is polymorphic -- if this function is called to process a deferred
1325 1280 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1326 1281 * the irq pointer is retrieved. If not doing deferred reprogramming,
1327 1282 * p is of the type 'apic_irq_t *'.
1328 1283 *
1329 1284 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1330 1285 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1331 1286 * taken offline after a cpu is selected, but before apic_rebind is called to
1332 1287 * bind interrupts to it.
1333 1288 */
1334 1289 int
1335 1290 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1336 1291 {
1337 1292 apic_irq_t *irqptr;
1338 1293 struct ioapic_reprogram_data *drep = NULL;
1339 1294 int rv;
1340 1295
1341 1296 if (deferred) {
1342 1297 drep = (struct ioapic_reprogram_data *)p;
1343 1298 ASSERT(drep != NULL);
1344 1299 irqptr = drep->irqp;
1345 1300 } else
1346 1301 irqptr = (apic_irq_t *)p;
1347 1302
1348 1303 ASSERT(irqptr != NULL);
1349 1304
1350 1305 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1351 1306 if (rv) {
1352 1307 /*
1353 1308 * CPU is not up or interrupts are disabled. Fall back to
1354 1309 * the first available CPU
1355 1310 */
1356 1311 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1357 1312 drep);
1358 1313 }
1359 1314
1360 1315 return (rv);
1361 1316 }
1362 1317
1363 1318
1364 1319 uchar_t
1365 1320 apic_modify_vector(uchar_t vector, int irq)
1366 1321 {
1367 1322 apic_vector_to_irq[vector] = (uchar_t)irq;
1368 1323 return (vector);
1369 1324 }
1370 1325
1371 1326 char *
1372 1327 apic_get_apic_type(void)
1373 1328 {
1374 1329 return (apic_psm_info.p_mach_idstring);
1375 1330 }
1376 1331
1377 1332 void
1378 1333 x2apic_update_psm(void)
1379 1334 {
1380 1335 struct psm_ops *pops = &apic_ops;
1381 1336
1382 1337 ASSERT(pops != NULL);
1383 1338
1384 1339 pops->psm_intr_exit = x2apic_intr_exit;
1385 1340 pops->psm_setspl = x2apic_setspl;
1386 1341
1387 1342 pops->psm_send_ipi = x2apic_send_ipi;
1388 1343 send_dirintf = pops->psm_send_ipi;
1389 1344
1390 1345 apic_mode = LOCAL_X2APIC;
1391 1346 apic_change_ops();
1392 1347 }
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