86 #define APIC_INT_VECT0 0xd4
87 #define APIC_INT_VECT1 0xd8
88 #define APIC_ERR_VECT 0xdc
89
90 /* IPL for performance counter interrupts */
91 #define APIC_PCINT_IPL 0xe
92 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */
93
94 /* Initial Count register */
95 #define APIC_INIT_COUNT 0xe0
96
97 /* Current Count Register */
98 #define APIC_CURR_COUNT 0xe4
99 #define APIC_CURR_ADD 0x39 /* used for remote read command */
100 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT)
101
102 /* Divider Configuration Register */
103 #define APIC_DIVIDE_REG 0xf8
104
105 /* Various mode for local APIC. Modes are mutually exclusive */
106 #define APIC_IS_DISABLED 0x0
107 #define APIC_MODE_NOTSET 0x1
108 #define LOCAL_APIC 0x2
109 #define LOCAL_X2APIC 0x3
110
111 /* x2APIC SELF IPI Register */
112 #define X2APIC_SELF_IPI 0xFC
113
114 /* General x2APIC constants used at various places */
115 #define APIC_SVR_SUPPRESS_BROADCAST_EOI 0x1000
116 #define APIC_DIRECTED_EOI_BIT 0x1000000
117
118 /* IRR register */
119 #define APIC_IRR_REG 0x80
120
121 /* ISR register */
122 #define APIC_ISR_REG 0x40
123
124 #define APIC_IO_REG 0x0
125 #define APIC_IO_DATA 0x4
126 #define APIC_IO_EOI 0x10
127
128 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */
129 #define APIC_ID_BIT_OFFSET 24
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86 #define APIC_INT_VECT0 0xd4
87 #define APIC_INT_VECT1 0xd8
88 #define APIC_ERR_VECT 0xdc
89
90 /* IPL for performance counter interrupts */
91 #define APIC_PCINT_IPL 0xe
92 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */
93
94 /* Initial Count register */
95 #define APIC_INIT_COUNT 0xe0
96
97 /* Current Count Register */
98 #define APIC_CURR_COUNT 0xe4
99 #define APIC_CURR_ADD 0x39 /* used for remote read command */
100 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT)
101
102 /* Divider Configuration Register */
103 #define APIC_DIVIDE_REG 0xf8
104
105 /* Various mode for local APIC. Modes are mutually exclusive */
106 enum apic_mode {
107 APIC_IS_DISABLED,
108 APIC_MODE_NOTSET,
109 LOCAL_APIC,
110 LOCAL_X2APIC,
111 };
112
113 /* x2APIC SELF IPI Register */
114 #define X2APIC_SELF_IPI 0xFC
115
116 /* General x2APIC constants used at various places */
117 #define APIC_SVR_SUPPRESS_BROADCAST_EOI 0x1000
118 #define APIC_DIRECTED_EOI_BIT 0x1000000
119
120 /* IRR register */
121 #define APIC_IRR_REG 0x80
122
123 /* ISR register */
124 #define APIC_ISR_REG 0x40
125
126 #define APIC_IO_REG 0x0
127 #define APIC_IO_DATA 0x4
128 #define APIC_IO_EOI 0x10
129
130 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */
131 #define APIC_ID_BIT_OFFSET 24
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